Google Picks Intel EMIB-T for Humufish TPU; TSMC CoWoS Constraint Forces Packaging Pivot
If EMIB-T wins the hyperscaler design cycle, Intel's packaging margin improves sharply — the service carries 35-45% gross margin versus foundry's 20-25%. But execution risk is real: Intel's packaging yield on advanced chiplets (5nm-equivalent density) has historically lagged TSMC's by 200-400 basis points.
A single yield miss on an early Humufish lot could reverse the entire narrative and lock Google back into CoWoS for future generations. The second-order effect: TSMC's CoWoS pricing power weakens if Intel proves reliable at scale, forcing TSMC to cut lead times or rates — a margin compression that flows directly into their gross profit guidance, which has already guided down 3 points YoY.
Intel's packaging business has spent three years chasing a use case.
If Google's selection holds and spreads to other AI accelerator designs, Intel shifts from a legacy node foundry into a critical path supplier for the training silicon that shapes the AI arms race — a $40B+ annual market where TSMC currently owns the packaging bottleneck. The mechanism: CoWoS-L has a 12-18 month lead time and costs 40-60% more than EMIB-T for comparable chiplet density.
Google's choice signals that margin pressure on AI infrastructure drives architecture decisions, not just performance. Watch whether other hyperscalers (Meta, Microsoft, Amazon) announce similar pivots at their next earnings calls or infrastructure summits — that would confirm the bottleneck is real, not a one-off.
Has Intel actually secured volume commitments from Google for Humufish production, or is this a design-phase evaluation that could revert to TSMC if CoWoS capacity opens up by tapeout?
Fault Lines
Strategic intelligence, synthesized daily — with a public track record. Every call graded against what actually happened.